Boolean Satisfiability in Electronic Design Automation

Boolean Satisjiability (SAT) is often used as the underlying model for a signijicant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other jields of Computer Science and Engineering. In recent years, new and efJicient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT " packages " are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. This tutorial paper is aimed at introducing the EDA professional to the Boolean satisjiability problem. Specijically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation , logic optimization, combinational equivalence checking , bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used f o r solving SAT, including those that have seen widespread use in specijic EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks.